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? freescale semiconductor, inc., 2004, 2005, 2006, 2007. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc13191 rev. 1.5, 03/2007 mc13191 package information plastic package case 1311-03 (qfn-32) scale 1:1 ordering information device device marking package mc13191 13191 qfn-32 1 introduction the mc13191 is a short range, low power, 2.4 ghz industrial, scientific, and medical (ism) band transceiver. the mc13191 contains a complete packet data modem which is co mpliant with the ieee ? 802.15.4 standard phy (physical) layer. this allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation form at. for full 802.15.4 standard compliance, the mc13192 and freescale's 802.15.4 mac software are required. when combined with an a ppropriate microcontroller (mcu), the mc13191 provides a cost-effective solution for short-range data links and networks. interface with the mcu is accomplished using a four wire serial peripheral interface (spi) c onnection and an interrupt request output which allows for the use of a variety of processors. the software and processor can be scaled to fit applications ranging from si mple point-to-point to star networks. mc13191 2.4 ghz ism band low power transceiver contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . 3 4 data transfer mode . . . . . . . . . . . . . . . . . . . . 4 5 electrical characteristics . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . 9 7 pin connections . . . . . . . . . . . . . . . . . . . . . . 12 8 applications information . . . . . . . . . . . . . . . 16 9 packaging information . . . . . . . . . . . . . . . . . 22
mc13191 technical data, rev. 1.5 2 freescale semiconductor for more detailed information about mc13191 operation, refer to the mc13191 reference manual , (mc13191rm). applications include, but are not limited to, the following: ? remote control and wire repla cement in industrial systems such as wireless sensor networks ? factory automation and motor control ? energy management (l ighting, hvac, etc.) ? asset tracking and monitoring potential consumer ap plications include: ? home automation and control (l ighting, thermostats, etc.) ? human interface devices (keyboard, mice, etc.) ? remote control ? wireless toys the transceiver includes a low noise amplifier, 1.0 mw power amplifier (pa), pll wi th internal voltage controlled oscillator (vco), on-boa rd power supply regulation, and fu ll spread-spectrum encoding and decoding. the device supports 250 kbps offset-qua drature phase shift keyi ng (o-qpsk) data in 2.0 mhz channels with 5.0 mhz channel spacing. the spi port and interrupt request output are used for receive (rx) and transmit (tx) data transfer and control. 2features ? 802.15.4 standard compliant tran sceiver supports 250 kbps o-qpsk data in 5.0 mhz channels and full spread-spectrum encode/decode ? operates on one of 16 selectable channels in the 2.4 ghz band ? receive sensitivity of <-91 dbm (t ypical) at 1.0% packet error rate ? recommended power supply range: 2.0 to 3.4 v ? 0 dbm nominal output pow er, programmable from - 27 dbm to 4 dbm typical ? buffered transmit and receive data packet s for simplified use with low cost mcus ? three power down modes for increased battery life: ? < 1.0 a off current ? 2.3 a typical hibernate current ? 35 a typical doze current (no clko) ? two internal timer comparators av ailable to supplement mcu resources ? programmable frequency clock output (clko) for use by mcu ? onboard trim capability for 16 mhz crystal referen ce oscillator eliminates the need for external variable capacitors and allows for automated production fre quency calibration. ? seven general purpose input/output (gpio) signals ? operating temperature range: -40 c to +85 c ? small form factor qfn-32 package
mc13191 technical data, rev. 1.5 freescale semiconductor 3 ? rohs compliant ? meets moisture sensitivity level 3 (msl3) ? 260 c peak reflow temperature ? meets lead-free requirements 2.1 software support freescale provides a software suite to complement the mc13191 hardware which is called the freescale simple media access controller (smac): ? simple proprietary wireless connectivity ? small memory footprint (about 3 kbytes typical) ? supports point-to-point and st ar network configurations ? proprietary networks ? source code and applicat ion examples provided 3 block diagrams figure 1 shows a simplified block diag ram of the mc13191 transceiver that meets the requirements of the 802.15.4 phy. figure 1. mc13191 simplified block diagram phase shift modulator rst gpio1 gpio2 gpio3 gpio4 xtal2 xtal1 rfin- rfin+ pao+ pao- mosi miso spiclk rxtxen ce attn gpio5 gpio6 gpio7 receive packet ram transmit packet ram 1 transmit ram arbiter receive ram arbiter pa vco crystal oscillator sy mbol generation fcs generation header generation mux sequence manager (control logic) vddlo2 4 256 mhz 2.45 ghz lna 1st if mix er if = 65 mhz 2nd if mix er if = 1 m hz pma decim ation filter matched filter baseband mixer dc d correlator symbol synch & det cca packet processor ir q arbiter 24 bit ev ent timer ir q 16 mhz agc analog regulator vbatt digital regulator l digital regulator h pow er-up control logic crystal regulator vco regulator vddint programmable prescaler clko 2 programmable timer comparators synthesizer vddd vddvco serial peripheral interface (spi) vdda vddlo1
mc13191 technical data, rev. 1.5 4 freescale semiconductor figure 2 shows the basic system block diagram for th e mc13191 in an application. interface with the transceiver is accomplished through a 4-wire spi port and inte rrupt request line. the media access control (mac), drivers, and network and a pplication software (as required) re side on the host processor. the host can vary from a simple 8-bit devi ce up to a sophisticated 32-bit processor depending on application requirements. figure 2. system level block diagram 4 data transfer mode the mc13191 has a data transfer mo de called packet mode where data is buffered in on-chip packet rams. there is a tx pack et ram and an rx packet ram, each of which are 64 locations by 16 bits wide. 4.1 packet structure figure 3 shows the packet structure of the mc13191 wh ich is consistent with the 802.15.4 standard. payloads of up to 125 bytes are supported. the mc13191 adds a four-byte preamble, a one-byte start of frame delimiter (sfd), and a one- byte frame length indicat or (fli) before the data. a two-byte frame check sequence (fcs) is calculated a nd appended to the end of the data. figure 3. mc13191 packet structure analog receiver mc13191 frequency generation analog transmitter voltage regulators power up management control logic buffer ram digital transceiver spi and gpio microcontroller spi rom (flash) ram cpu a/d timer application irq arbiter ram arbiter timer network mac phy driver preamble sfd fli payload data fcs 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
mc13191 technical data, rev. 1.5 freescale semiconductor 5 4.2 receive path description in the receive signal path, the rf input is converted to low if in-phase and qu adrature (i & q) signals through two down-conversion stages. an energy de tect can be performed based upon the baseband energy integrated over a specific time interval. the di gital back end performs di fferential chip detection (dcd), the correlator ?de-spr eads? the direct sequence spread spectrum (dsss) offset qpsk (o-qpsk) signal, determines the symbol s and packets, and detects the data. the preamble, sfd, and fli are parsed and used to de tect the payload data and fcs which are stored in ram. a two-byte fcs is calculated on the received da ta and compared to the fcs value appended to the transmitted data which generates a cyclical redundancy check (crc) re sult. link quality is measured over a 64 s period after the packet preamble and stored in ram. the mc13191 uses a packet m ode where the data is processed as an entire packet and stored in rx packet ram. the mcu is notified that an entire p acket has been receiv ed via an interrupt. figure 4 shows energy detection reporte d power versus input power. note the 802.15.4 standard accuracy and range limits are shown for reference. figure 4. reported power level versus input power for ed or lqi 4.3 transmit path description for the transmit path, the tx data th at was previously stored in tx pa cket ram is retrieved, formed into packets, spread, and then up-conve rted to the transmit frequency. because the mc13191 is used in packet mode, data is proc essed as an entire packet. the data is first loaded into the tx buffer. the mcu then requests that the mc13191 transmit the data. the mcu is notified via an interrupt when the whole packet has successfully been transmitted. -85 -75 -65 -55 -45 -35 -25 -15 -85 -75 -65 -55 -45 -35 -25 -15 input power level (dbm) reported power level (dbm) 802.15.4 accuracy and range requirements
mc13191 technical data, rev. 1.5 6 freescale semiconductor 5 electrical characteristics 5.1 maximum ratings 5.2 recommended oper ating conditions table 1. absolute maximum ratings rating symbol value unit power supply voltage v batt, v ddint -0.3 to 3.6 vdc digital input voltage vin -0.3 to (v ddint + 0.3) rf input power p max 10 dbm junction temperature t j 125 c storage temperature range t stg -55 to 125 c note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to t he limits in the electrical characteristics or recommended operating conditions tables. note: esd protection meets human body model (hbm) = 2 kv. rf input/output pins have no esd protection. table 2. recommended operating conditions characteristic symbol min typ max unit power supply voltage (v batt = v ddint ) 1 1 if the supply voltage is produced by a s witching dc-dc converter, ripple should be less than 100 mv peak-to-peak. v batt, v ddint 2.0 2.7 3.4 vdc input frequency f in 2.405 - 2.480 ghz ambient temperature range t a -40 25 85 c logic input voltage low v il 0-30% v ddint v logic input voltage high v ih 70% v ddint -v ddint v spi clock rate f spi --8.0mhz rf input power p max - - 10 dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 16 mhz only
mc13191 technical data, rev. 1.5 freescale semiconductor 7 5.3 dc electrical characteristics table 3. dc electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply current (v batt + v ddint ) off 1 hibernate 1 doze (no clko) 1 2 idle transmit mode (0 dbm nominal output power) receive mode 1 to attain specified low power current, all gpio and other digital io must be handled properly. see section 8.4, ?low power considerations? . 2 clko frequency at default value of 32.786 khz. i leakage i cch i ccd i cci i cct i ccr - - - - - - 0.2 1.0 35 500 30 37 1.0 6.0 102 800 35 42 a a a a ma ma input current (v in = 0 v or v ddint ) (all digital inputs) i in --1 a input low voltage (all digital inputs) v il 0-30% v ddint v input high voltage (all digital inputs) v ih 70% v ddint -v ddint v output high voltage (i oh = -1 ma) (all digital outputs) v oh 80% v ddint -v ddint v output low voltage (i ol = 1 ma) (all digital outputs) v ol 0-20% v ddint v
mc13191 technical data, rev. 1.5 8 freescale semiconductor 5.4 ac electrical characteristics note all ac parameters measured with spi registers at defaul t settings except where noted and the following registers over-programmed: register 08 = 0xfff7 and register 11 = 0x20ff table 4. receiver ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted. parameters measured at connector j6 of evaluation circuit.) characteristic symbol min typ max unit sensitivity for 1% pa cket error rate (per ) (-40 to +85 c) sens per --92-dbm sensitivity for 1% pa cket error rate (per ) (+25 c) - -92 -82 dbm saturation (maximum input level) sens max 010 -dbm channel rejection for 1% per (desired signal -82 dbm) +5 mhz (adjacent channel) -5 mhz (adjacent channel) +10 mhz (alternate channel) -10 mhz (alternate channel) >= 15 mhz - - - - - 25 31 42 41 49 - - - - - db db db db db frequency error tolerance (total) - - 200 khz symbol rate error tolerance - - 80 ppm table 5. transmitter ac electrical characteristics (vbatt, vddint = 2.7 v, ta = 25 c, fr ef = 16 mhz, unless otherwise noted. parameters measured at connector j5 of evaluation circuit.) characteristic symbol min typ max unit power spectral density (-40 to +85 c) absolute limit - -47 - dbm power spectral density (-40 to +85 c) relative limit - 47 - nominal output power 1 1 spi register 12 programmed to 0x00bc which se ts output power to nominal (0 dbm typical). p out -5 0 - dbm maximum output power 2 2 spi register 12 programmed to 0x00ff which sets output power to maximum. 4dbm error vector magnitude evm - 20 45 % output power control range (-27 dbm to +4 dbm typical) - 31 - db over the air data rate - 250 - kbps spurious emissions - -56 -40 dbm 2nd harmonic - -42 - dbc 3rd harmonic - -44 - dbc
mc13191 technical data, rev. 1.5 freescale semiconductor 9 figure 5 shows a typical ac para meter evaluation circuit. figure 5. ac paramete r evaluation circuit table 6. digital timing specifications (vbatt, vddint = 2.7 v, ta = 25 c, fr ef = 16 mhz, unless otherwise noted. spi timing parameters are referenced to figure 7 .) symbol parameter min typ max unit t0 spiclk period 125 ns t1 pulse width, spiclk low 50 ns t2 pulse width, spiclk high 50 ns t3 delay time, miso data valid from falling spiclk 15 ns t4 setup time, ce low to rising spiclk 15 ns t5 delay time, miso valid from ce low 15 ns t6 setup time, mosi valid to rising spiclk 15 ns t7 hold time, mosi valid from rising spiclk 15 ns rst minimum pulse width low (asserted) 250 ns j4 clock sel 1 2 miso r3 10k rxd j2 header 10x2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 spi_clk gpio1 l2 6.8nh t2 2450bl15b200 1 3 2 5 4 r5 47k gpio2 r2 200 + c2 220pf u1 mc13192 16 20 14 22 3 5 7 27 9 13 19 24 18 17 4 6 8 26 10 23 15 21 25 11 12 1 28 2 29 30 31 32 spiclk irq attn vddint gnd pao+ gnd xtal2 gpio3 rxtxen ce gpio6 miso mosi gnd pao- gpio4 xtal1 gpio2 gpio5 clko vddd gpio7 gpio1 rst rfin- vddlo2 rfin+ vddlo1 vddvco vbatt vdda r1 47k r6 47k r4 47k abel reset c7 10pf + c1 220pf c4 9pf c5 9pf j3 wake up 1 2 attn j6 sma 1 2 j5 sma 1 2 + c3 220pf gpio2 j7 reset 1 2 3 t1 2450bl15b200 1 3 2 5 4 clko c8 10pf mosi gpio1 vcc y1 tsx-10a@16mhz baud sel pa2 j1 mcu interface 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 c6 0.1uf rtxeni l1 8.2nh mcu reset ce irq rtxeni 16 mhz clk
mc13191 technical data, rev. 1.5 10 freescale semiconductor 6 functional description 6.1 mc13191 operational modes the mc13191 has a number of operati onal modes that allow for low-cu rrent operation. transition from the off mode to idle mode occurs when rst is negated. once in idle mode, the spi is active and controls the ic. transition to hibe rnate and doze modes is enabled via the spi. table 7 summarizes these modes, along with the transition times while table 3 lists current drain in the various modes. 6.2 serial peripheral interface (spi) the host microcontroller directs th e mc13191, checks its status, and re ads/writes data to the device through the 4-wire spi port. the transceiver operates as an spi slave device only. a transaction between the host and the mc13191 occurs as multiple 8-bit bursts on the spi. the spi signals are: 1. chip enable (ce ) - a transaction on the spi port is framed by the active low ce input signal. a transaction is a minimum of 3 spi bursts a nd can extend to a greater number of bursts. 2. spi clock (spiclk) - the host drives the spicl k input to the mc13191. data is clocked into the master or slave on the leading (rising) edge of the return-to-zero spiclk and data out changes state on the trailing (falling) edge of spiclk. note for freescale microcontrollers, the spi clock format is the clock phase control bit cpha = 0 and the clock polarity control bit cpol = 0. 3. master out/slave in (mosi) - incoming data from the host is presented on the mosi input. 4. master in/slave out (miso) - the mc13191 pres ents data to the master on the miso output. a typical interconnection to a microcontroller is shown in figure 6 . table 7. mc13191 mode definitions and transition times mode definition transition time to or from idle off all ic functions off, leakage only. rst asserted. digital outputs are tri-stated including irq 10 - 25 ms to idle hibernate crystal reference oscillator off. (spi not functional.) ic responds to attn . data is retained. 7 - 20 ms to idle doze crystal reference oscillator on but clko output available only if register 7, bit 9 = 1 for frequencies of 1 mhz or less. (spi not functional.) responds to attn and can be programmed to enter idle mode through an internal timer comparator. (300 + 1/clko) s to idle idle crystal reference oscillator on with cl ko output available. spi active. receive crystal reference oscillator on. receiver on. 144 s from idle transmit crystal reference oscillator on. transmitter on. 144 s from idle
mc13191 technical data, rev. 1.5 freescale semiconductor 11 figure 6. spi interface although the spi port is fully st atic, internal memory, timer, and interr upt arbiters require an internal clock (clk core ) derived from the crystal reference oscillator, to communicate from the spi registers to internal registers and memory. 6.2.1 spi burst operation the spi port of an mcu transfers data in bursts of 8 bi ts with most significant bit (msb) first. the master (mcu) can send a byte to the slave (transceiver) on the mosi line and the slave can send a byte to the master on the miso line . although an mc13191 transact ion is three or more spi bursts long, the timing of a single spi burst is shown in figure 6 . figure 7. spi single burst timing diagram. spi digital timing specifications are shown in table 6 . shift register baud rate generator shift register chip enable (ce) rxd miso txd mosi sclk spiclk mcu mc13191 ce 1 2345 678 ce spiclk t1 t2 t4 t0 spi burst valid t5 t6 t3 valid t7 mi so mosi valid
mc13191 technical data, rev. 1.5 12 freescale semiconductor 6.2.2 spi transaction operation although the spi port of an mcu transfers data in bur sts of 8 bits, the mc13191 requires that a complete spi transaction be framed by ce , and there will be three (3) or more bursts per transaction. the assertion of ce to low, signals the start of a tr ansaction. the first spi burst is a write of an 8-bit header to the transceiver (mosi is valid) that defines a 6-bit address of the in ternal resource being accessed and identifies the access as being a read or write operation. in this context, a write consists of data written to the mc13191 and a read consists of data written to the spi master. the fo llowing spi bursts will be either the write data (mosi is valid) to the transceiver or read data from the transceiver (miso is valid). although the spi bus is capable of sending data simultaneously betw een master and slave, the mc13191 never uses this mode. the number of data bytes (paylo ad) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. after the final spi burst, ce is negated to high to signal the end of the transaction. refer to the mc13191 reference manual , (mc13191rm) for more details on spi registers and transaction types. an example spi read transaction wi th a 2-byte payload is shown in figure 8 . figure 8. spi read transaction diagram 7 pin connections table 8. pin function description pin # pin name type description functionality 1 rfin- rf input lna negative differential input. 2 rfin+ rf input lna positive differential input. 3 not used tie to ground. 4 not used tie to ground. 5 pao+ rf output /dc input power amplifier positive outp ut. open drain. connect to v dda . 6 pao- rf output/dc input power amplifier negative output. open drain. connect to v dda . 7 sm test mode pin. tie to ground tie to ground for normal operation ce spiclk miso mosi valid valid valid clock burst header read data
mc13191 technical data, rev. 1.5 freescale semiconductor 13 8 gpio4 1 digital input/ output general purpose input/output 4. see footnote 1 9 gpio3 1 digital input/ output general purpose input/output 3. see footnote 1 10 gpio2 1 digital input/ output general purpose inpu t/output 2. when gpi o_alt_en, register 9, bit 7 = 1, gpio2 functions as a ?crc valid? indicator. see footnote 1 11 gpio1 1 digital input/ output general purpose inpu t/output 1. when gpi o_alt_en, register 9, bit 7 = 1, gpio1 functions as an ?out of idle? indicator. see footnote 1 12 rst digital input active low reset. while held low, the ic is in off mode and all internal information is lost fr om ram and spi registers. when high, ic goes to idle mode, with spi in default state. 13 rxtxen 2 digital input active high. low to high transition initiates rx or tx sequence depending on spi setting. should be taken high after spi programming to start rx or tx sequence and should be held high through the sequence. after sequence is complete, return rxtxen to low. when held low, forces idle mode. see footnote 2 14 attn 2 digital input active low attention. transitions ic from either hibernate or doze modes to idle. see footnote 2 15 clko digital output clock output to host mcu. programmable frequencies of: 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, 62.5 khz, 32.786+ khz (default), and 16.393+ khz. 16 spiclk 2 digital clock input external clock input for the spi interface. see footnote 2 17 mosi 2 digital input master out/slave in. dedicated spi data input. see footnote 2 18 miso 3 digital output master in/slave out. dedicated spi data output. see footnote 3 19 ce 2 digital input active low chip enable. enables spi transfers. see footnote 2 20 irq digital output active low interrupt request. open drain device. programmable 40 k ? internal pull-up. interrupt can be serviced every 6 s with <20 pf load. optional external pull-up must be >4 k ? . 21 vddd power output digital regulated supply bypass. decouple to ground. 22 vddint power input digital interface supply & digital regulator input. connect to battery. 2.0 to 3.4 v. decouple to ground. 23 gpio5 1 digital input/output general purpose input/output 5. see footnote 1 24 gpio6 1 digital input/output general purpose input/output 6. see footnote 1 25 gpio7 1 digital input/output general purpose input/output 7. see footnote 1 26 xtal1 input crystal reference oscillator input. connect to 16 mhz crystal and load capacitor. table 8. pin function description (continued) pin # pin name type description functionality
mc13191 technical data, rev. 1.5 14 freescale semiconductor 27 xtal2 input/output crystal reference oscillator output note: do not load this pin by using it as a 16 mhz source. measure 16 mhz output at pin 15, clko, programmed for 16 mhz. see the mc13191 reference manual for details. connect to 16 mhz crystal and load capacitor. 28 vddlo2 power input lo2 vdd supply. connect to vdda externally. 29 vddlo1 power input lo1 vdd supply. connect to vdda externally. 30 vddvco power output vco regulated supply bypass. decouple to ground. 31 vbatt power input analog voltage regulators input. connect to battery. decouple to ground. 32 vdda power output analog regulated supply output. connect to directly vddlo1 and vddlo2 externally and to pao through a frequency trap. note: do not use this pin to supply circuitry external to the chip. decouple to ground. ep ground external paddle / flag ground. connect to ground. 1 the transceiver gpio pins default to inputs at reset. ther e are no programmable pullups on these pins. unused gpio pins should be tied to ground if left as inputs, or if left unconn ected, they should be programmed as outputs set to the low state. 2 during low power modes, input must remain driven by mcu. 3 by default miso is tri-stated when ce is negated. for low power operation, miso_hi z_en (bit 11, register 07) should be set to zero so that miso is driven low when ce is negated. table 8. pin function description (continued) pin # pin name type description functionality
mc13191 technical data, rev. 1.5 freescale semiconductor 15 figure 9. pin connections (top view) 1 2 3 gpio3 gpio2 gpio1 rst rxtxen attn clko spiclk 4 5 6 7 8 nc rfin+ nc pao+ pao- nc gpio4 rfin- vddint gpio5 vddd irq ce miso mosi gpio6 12 13 14 15 16 11 10 9 24 23 22 21 20 19 18 17 vdda vbatt vddvco vddlo1 vddlo2 xtal2 xtal1 gpio7 ep 29 28 27 26 25 30 31 32 mc13191
mc13191 technical data, rev. 1.5 16 freescale semiconductor 8 applications information this section provides application sp ecific information regarding crysta l oscillator refe rence frequency, a basic design example for interfacing the mc 13191 to an mcu and recommended crystal usage. 8.1 crystal oscillator reference frequency for low long term drift, users may require that se veral frequency tolerances be kept as low as 40 ppm accuracy. this means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. the mc13191 tr ansceiver provides onboard crystal trim capacitors to assist in meeting this performance. the primary determining factor in me eting this specification is the to lerance of the crystal oscillator reference frequency. a number of factors exist that cont ribute to this tolerance a nd a crystal specification will quantify each of them: 1. the initial (or make) tolerance of the crystal resonant frequency itself. 2. the variation of the crystal res onant frequency with temperature. 3. the variation of the crystal resonant frequency with time , also commonly known as aging. 4. the variation of the crystal re sonant frequency with load cap acitance, also commonly known as pulling. this is affected by: a) the external load capacitor values - init ial tolerance and variation with temperature. b) the internal trim capacitor values - initial tolerance and variation with temperature. c) stray capacitance on the crystal pin nodes - incl uding stray on-chip capaci tance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. freescale requires the use of a 16 mhz crystal with a <9 pf load capacitance. the mc13191 does not contain a reference divider, so 16 mhz is the only frequency that can be used. a crysta l requiring higher load capacitance is prohibited because a higher lo ad on the amplifier circuit may compromise its performance. the crystal manuf acturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. the osci llator amplifier configuration used in the mc13191 requires two balanced load capacitors from each terminal of the crysta l to ground. as such, the capacitors are seen to be in series by the crystal, so each must be <18 pf for proper loading. in the reference schematic, the external load capacito rs are shown as 6 .8 pf each, used in conjunction with a crystal that requires an 8 pf load capacitance. the default internal trim capaci tor value (2.4 pf) and stray capacitance total value (6.8 pf) sum up to 9.2 pf for a total of 16 pf. the value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. a different board layout may re quire a different external load cap acitor value. the on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the spi and observing the frequency at clko. each internal trim load capacitor has a trim range of approximately 5 pf in 20 ff steps. initial tolerance for the internal trim capacitance is approximately 15%.
mc13191 technical data, rev. 1.5 freescale semiconductor 17 because the mc13191 contains an on-chip reference fre quency trim capability, it is possible to trim out virtually all of the initial tole rance factors and put th e frequency within 0.12 ppm on a board-by-board basis. a tolerance analysis budget may be created using all the previously stated factors. it is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using rss (root-sum-squa re) analysis. the aging factor is usually specified in pp m/year and the product designer can dete rmine how many years are to be assumed for the product lifetime. taki ng all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the desired specification. 8.2 design example figure 10 shows a basic application schematic fo r interfacing the mc13191 with an mcu. table 9 lists the bill of materials (bom). the mc13191 has differential rf inputs and outputs that are well suited to balanced printed wire antenna structures. alternatively, as in the application circui t, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip ba luns or microstrip equivalents. pao+ and pao- require a dc c onnection to vdda (the analog re gulator output) through ac blocking elements. this is accompl ished through the baluns in the referenced design. the 16 mhz crystal should be mount ed close to the mc13191 because th e crystal trim default assumes that the listed kds daishinku crystal (see table 10 ) and the 6.8 pf load capacitors shown are used. if a different crystal is use d, it should have a specified load cap acitance (stray capac itance, etc.) of 9 pf or less. other crystals are listed in section 8.3, ?crystal requirements? . vdda is an analog regulator output used to supply only the onboard pa (pao+ and pao-) and vddlo1 and vddlo2 pins. vdda should not be used to power devices external to the transceiver chip. bypassing capacitors are critical and should be placed close to the device. unus ed pins should be grounded as shown. the spi connections to the mcu include ce , mosi, miso, and spiclk. the spi can run at a frequency of 8 mhz or less. optionally, clko can provide a clock to the mcu. the clko frequency is programmable via the spi a nd has a default of 32.786+ khz (16 mhz / 488). the attn line can be driven by a gpio from the mcu (as shown) or can also be c ontrolled by a switch or other hardware. the latter approach allows the mcu to be put into a sleep mode and then awakened by clko when the attn line wakes up the mc13191. rxtxen is used to initiate re ceive, transmit or cca/ed sequences under mcu control. in this case, rxtxen mu st be controlled by an mcu gpio with the connecti on shown. device reset (rst ) is controlled through a connection to an mcu gpio.
mc13191 technical data, rev. 1.5 18 freescale semiconductor figure 10. mc13191 configured with a mcu mcu mosi ic2 pg 2012tk-e2 6 5 4 1 3 2 vdd in vcont out1 out2 gnd 50_ohm4 c7 10pf l2 8.2nh ant1 f_antenna x1 16.000mhz 100_ohm3 c1 1f vdda miso 3v0_rf ss gpio gpio 50_ohm3 irq 50_ohm1 50_ohm2 gpio 100_ohm2 50_ohm7 gpio r3 0 r2 0 r1 470k c4 220nf c12 0.5pf vdda c3 220nf c8 10pf gpio z1 ldb212g4020c-001 5 1 6 2 3 4 c2 220nf l1 6.8nh c6 6.8pf c9 10pf z2 ldb212g4020c-001 5 1 6 2 3 4 c11 10pf gpio c5 6.8pf 3v0_bb j1 sma receptacle, female 1 2 5 3 4 50_ohm6 clk ic1 mc13191 14 19 15 11 10 9 8 25 23 24 20 18 17 6 5 1 2 12 13 7 16 4 3 26 27 31 32 21 22 29 28 30 ep attnb ceb clko gpio1 gpio2 gpio3 gpio4 gpio7 gpio5 gpio6 irqb miso mosi pao_m pao_p rin_m rin_p rstb rxtxen not used spiclk not used not used xtal1 xtal2 vbatt vdda vddd vddint vddlo1 vddlo2 vddvco gnd 100_ohm4 l3 8.2nh c10 10pf sclk 100_ohm1
mc13191 technical data, rev. 1.5 freescale semiconductor 19 thhht 8.3 crystal requirements the suggested crystal specificat ion for the mc13191 is shown in table 10 . a number of the stated parameters are related to desired package, desired te mperature range and use of crystal capacitive load trimming. for more design details and su ggested crystals, see application note an3251, reference oscillator crystal requirements for mc1319x, mc1320x, and mc1321x . table 9. mc13191 to mcu bill of materials (bom) item quantity reference part manufacturer 1 1 ant1 f_antenna printed wire 21 c1 1 f 3 3 c2, c3, c4 220 nf 4 2 c5, c6 6.8 pf 5 5 c7, c8, c9, c10, c11 10 pf 6 1 c12 0.5 pf 7 1 ic1 mc13191 freescale semiconductor 81 ic2 pg2012tk-e2 nec 9 1 j1 sma receptacle, female 10 1 l1 6.8 nh 11 2 l2, l3 8.2 nh 12 1 r1 470 k ? 13 2 r2, r3 0 ? 14 1 x1 16.000 mhz, type dsx321g, zd00882 kds, daishinku corp 15 2 z1, z2 ldb212g4020c-001 murata table 10. mc13191 crystal specifications 1 parameter value unit condition frequency 16.000000 mhz frequency tolerance (cut tolerance) 2 10 ppm at 25 c frequency stability (temperature drift) 3 15 ppm over desired temperature range aging 4 2 ppm max equivalent series resistance 5 43 ? max load capacitance 6 5 - 9 pf shunt capacitance <2 pf max mode of oscillation fundamental
mc13191 technical data, rev. 1.5 20 freescale semiconductor 8.4 low power considerations ? program and use the modem io pi ns properly for low power operation ? all unused modem gpiox signals must be used one of 2 ways: ? if the off mode is to be us ed as a long term low power m ode, unused gpio should be tied to ground. the default gpio mode is an input and there will be no conflict. ? if only hibernate and/ or doze modes are used as long te rm low power modes, the gpio should programmed as outputs in the low state. ? when modem gpio are used as outputs: ? pullup resistors should be provi ded (can be provided by the mcu io pin if tied to the mcu) if the modem off condition is to be used as a long term low power mode. ? during hibernate and/or doze modes, the gp io will retain its programmed output state. ? if the modem gpio is used as an input, the gpio should be driven by its source during all low power modes or a pullup resi stor should be provided. ? digital outputs irq , miso, and clko: ? miso - is always an output. during hibern ate, doze, and active modes, the default condition is for the miso output to go to tristate when ce is de-asserted, and this can cause a problem with the mcu because one of its i nputs can float. program control_b register 07, bit 11, miso_hiz_en = 0 so that miso is driven low when ce is de-asserted. as a result, miso will not float when doze or hibernate mode is enabled. ?irq - is an open drain output (od) and shoul d always have a pullup resistor (typically provided by the mcu io). irq acts as the interrupt request output. note it is good practice to have the irq interrupt input to the mcu disabled during the hardware reset to the modem. after releasing the modem hardware reset, the interrupt request input to the mcu can then be enabled to await the irq that signifies the modem is re ady and in idle mode; this can prevent a possible extraneous false interrupt request. ? clko - is always an output. during hibernate clko retains it s output state, but does not toggle. during doze, clko may toggle de pending on whether it is being used. ? if the mcu is also going to be used in low power modes, be sure that all unused io are programmed properly for low power operation (t ypically best case is as outputs in the low state). the mc13191 is commonly used with the freescale mc9s 08gt/gb 8-bit devices. for these mcus: ? use only stop2 and stop3 modes (not stop1) wi th these devices where the gpio states are retained. the mcu must retain control of the mc13191 io during low power operation. 1 user must be sure manufacturer specif ications apply to the desired package. 2 a wider frequency tolerance may acceptable if app lication uses trimming at production final test. 3 a wider frequency stability may be acceptable if a pplication uses trimming at production final test. 4 a wider aging tolerance may be acceptable if applic ation uses trimming at production final test. 5 higher esr may be acceptable with lower load capacitance. 6 lower load capacitance can allow higher esr and is better for low temperature operation in doze mode.
mc13191 technical data, rev. 1.5 freescale semiconductor 21 ? as stated above all unused gp io should be programmed as out puts low for lowest power and no floating inputs. ? mc9s08gt devices have io signals that are not pinned-out on th e package. these signals must also be initialized (even though they ca nnot be used) to prevent floating inputs.
mc13191 technical data, rev. 1.5 22 freescale semiconductor 9 packaging information figure 11. outline dimens ions for qfn-32, 5x5 mm (case 1311-03, issue e) n exposed die attach pad 2.95 25 8 1 32 3.25 32x 0.18 0.30 24 17 16 9 0.5 m 0.1 c m 0.05 c a b 32x 0.5 0.3 c 0.1 a b c 0.1 a b view m-m 0.25 28x detail m pin 1 index 2.95 3.25 pin 1 index area 5 b c 0.1 2x 2x c 0.1 a 5 g m m 1.0 1.00 0.05 c 0.1 c 0.05 c seating plane 5 detail g view rotated 90 clockwise (0.5) (0.25) 0.8 0.75 0.00 (1.73) (0.25) 0.065 32x 0.015 (45 ) 5 4 preferred corner configuration detail n 0.60 0.24 0.60 0.24 4 detail n corner configuration option detail t detail m backside pin 1 index option detail t backside pin 1 index option (90 ) 5 2x 2x 0.39 0.31 0.1 0.0 detail m backside pin 1 index option 1.6 0.475 0.425 1.5 backside pin 1 index 0.25 0.15 r detail s detail m preferred backside pin 1 index 0.217 0.137 (0.25) 0.217 0.137 (0.1) detail s preferred backside pin 1 index notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. the complete jedec designator for this package is: hf-pqfp-n. 4. corner chamfer may not be present. dimensions of optional features are for reference only. 5. coplanarity applies to leads, corner leads, and die attach pad. 6. for anvil singulated qfn packages, maximum draft angle is 12.
notes mc13191 technical data, rev. 1.5 freescale semiconductor 23
document number: mc13191 rev. 1.5 03/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale se miconductor data sheets and /or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does no t convey any license under its patent rights nor the rights of others. freescale semiconductor prod ucts are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor pr oducts for any such unintended or unauthorized application, buyer shall indemnify and hold free scale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004, 2005, 2006, 2007. all rights reserved.

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